datasheet adsl vcxo clock source mk3732-07 idt? / ics? adsl vcxo clock source 1 mk3732-07 rev g 050203 description the mk3732-07 is a low cost, low jitter, high performance vcxo and pll clock synthesizer designed to replace expensive vcxo modules an d oscillators. the on-chip voltage controlled crystal osc illator (vcxo) ac cepts a 0 to 3.3 v input voltage to cause the output clocks to vary by + 100 ppm. using ics? patented vcxo and analog phase-locked loop (pll) techniques, the device uses an inexpensive 13.248 mhz pullable crystal input to produce one or two output clocks. the mk3732-07 is a pin-to-pin replacement for the mk2732-07 when using +3.3v supply voltage. ics manufactures the largest variety of xdsl clock synthesizers for all applicatio ns. consult ics to eliminate vcxos, crystals, and oscillators from your board. features ? packaged in 16 pin (150 mil) soic ? replaces a vcxo and oscillator ? ideal for asymmetrical digital subscriber line (adsl) chipsets ? uses an inexpensive pullable crystal ? on-chip patented vcxo with pull range of 200 ppm (+ 100 ppm) minimum ? vcxo tuning voltage of 0 to 3.3 v ? 12 ma output drive ca pability at ttl levels ? advanced, low power, sub-micron cmos process ? operating voltage of 3.3v ? industrial temperature range available block diagram voltage c ontrolled crystal oscillator x1 x2 vin 13.248 mhz p ullable crystal pll/ clock synthesis circuitry clk1 clk2 s2:s0 vdd gnd oe 3 3 3
mk3732-07 adsl vcxo clock source vcxo and synthesizer idt? / ics? adsl vcxo clock source 2 mk3732-07 rev g 050203 pin assignment clock select table 0=connect directly to gnd m=leave unconnected (floating) 1=connect directly to vdd pin descriptions 12 1 11 2 10 3 9 x2 4 x1 5 vdd 6 nc 7 vin 8 vdd gnd vdd gnd gnd s0 s2 clk1 oe 16 15 14 13 clk2 s1 16 pin (150 mil) soic s2 s1 s0 input clk1 clk2 0 0 0 13.248 35.328 29.4 0 0 m 13.248 35.328 47.1 0 0 1 13.248 35.328 40.4 0 1 0 13.248 42.4 35.328 0 1 m test test test 0 1 1 test test test 1 0 0 test test test 1 0 m test test test 1 0 1 13.248 35.328 off 1 1 0 13.248 2.208 off 1 1 m 13.248 24.73 35.328 1 1 1 13.248 49.46 35.328 pin number pin name pin type pin description 1 x2 input crystal connection. connect to a pullable crystal of 13.248 mhz. 2 x1 input crystal connection. connect to a pullable crystal of 13.248 mhz. 3,5,13 vdd power connect to +3.3v. 4 vin input voltage input to vcxo. zero to 3.3v signal which controls the vcxo frequency. 6,12,14 gnd power connect to ground. 7 clk1 output clock output #1 per table above. 8 clk2 output clock output #2 per table above. 9 s2 input select input #2. selects outputs per table above. internal pull-up resistor. 10 oe input output enable. tri-states outputs when low. internal pull-up resistor. 11 s0 input select input #0. selects outputs per table above. 15 nc - no connect. do not connect anything to this pin. 16 s1 input select input #1. selects outputs per table above.
mk3732-07 adsl vcxo clock source vcxo and synthesizer idt? / ics? adsl vcxo clock source 3 mk3732-07 rev g 050203 external component selection the mk3732-07 requires a minimum number of external components for proper operation. decoupling capacitors decoupling capacitors of 0.01 f should be connected between vdd and gnd on pins 3 and 6, on pins 5 and 6, and on pins 13 and 14, as close to the mk3732-07 as possible. for optimum device performance, the decoupling capacitors should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb traces between the clock outputs and the loads are over 1 inch, series termination should be used. to series terminate a 50 ? trace (a commonly used trace impedance) place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . quartz crystal the mk3732-07 vcxo function consists of the external crystal and the integrated vcxo oscillator circuit. to assure the best system performance (frequency pull range) and reliability, a crystal de vice with th e recommended parameters must be used, and the layout guidelines discussed in the following section must be followed. the frequency of oscilla tion of a quartz crystal is determined by its ?cut? and by the load capacitors connected to it. the mk3732-07 incorporates on-chip variable load capacitors that ?pull? (change) the frequency of the crystal. the crystal specified for use with the mk3732-07 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14pf. the external crystal must be connected as close to the chip as possible and should be on the same side of the pcb as the mk3732-07. there should be no via?s between the crystal pins and the x1 and x2 device pins. there should be no signal traces underneath or close to the crystal. please see application note man05 for recommended crystal parameters and suppliers. crystal tuning load capacitors the crystal traces should include pads for small fixed capacitors, one between x1 and ground, and another between x2 and ground. stuffing of these capacitors on the pcb is optional. the need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by pcb layout. the typical required capacitor value is 1 to 4 pf. the procedure for determining the value of these capacitors can be found in application note man05.
mk3732-07 adsl vcxo clock source vcxo and synthesizer idt? / ics? adsl vcxo clock source 4 mk3732-07 rev g 050203 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the mk3732-07. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=3.3v 5% , ambient temperature 0 to +70 c, unless stated otherwise item rating supply voltage, vdd 7v all inputs and outputs -0.5v to vdd+0.5v ambient operating temperature -40 to +85 c storage temperature -65 to +150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 ? +85 c power supply voltage (measured in respect to gnd) +3.15 +3.45 v reference crystal parameters refer to page 3 parameter symbol conditions min. typ. max. units operating voltage vdd 3.15 3.3 3.45 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v output high voltage (cmos level) v oh i oh = -8 ma vdd-0.4 v input high voltage, binary inputs v ih s2, s1, oe 2.0 v input high voltage, trinary input v ih s0 vdd-0.5 v input low voltage, binary inputs v il s2, s1, oe 0.8 v input low voltage, trinary input v il s0 0.5 v operating supply current idd no load 12 ma short circuit current i os 50 ma input capacitance s2:s0, oe 5 pf frequency synthesis error both clocks 0 ppm vin, vcxo control voltage v ia 03.3v
mk3732-07 adsl vcxo clock source vcxo and synthesizer idt? / ics? adsl vcxo clock source 5 mk3732-07 rev g 050203 ac electrical characteristics vdd = 3.3v 5% , ambient temperature 0 to +70 c, unless stated otherwise note 1: external pullable crystal must conf orm with those listed in application note man05 thermal characteristics parameter symbol conditions min. typ. max. units input crystal frequency f in 13.248 mhz output clock rise time t or 0.8 to 2.0v 1.5 ns output clock fall time t of 2.0 to 0.8v 1.5 ns output clock duty cycle t d at vdd/2 40 60 % maximum absolute jitter t j 150 ps phase noise, relative to carrier 10 khz offset -115 dbc/hz output pullab ility, note 1 f p 0v < vin < 3.3v 100 ppm parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 120 c/w ja 1 m/s air flow 115 c/w ja 3 m/s air flow 105 c/w thermal resistance junction to case jc 58 c/w
mk3732-07 adsl vcxo clock source vcxo and synthesizer idt? / ics? adsl vcxo clock source 6 mk3732-07 rev g 050203 package outline and package dimensions (16 pin soic) package dimensions are kept current with jedec publication no. 95 ordering information while the information presented herein has been checked for both a ccuracy and reliability, integrat ed circuit systems (ics) ass umes no responsibility for either its use or for the infringement of an y patents or other rights of third parties, which would result f rom its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves th e right to change any circuitr y or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. part / order number (note 1) marking shipping packaging package temperature mk3732-07s mk3732-07s tubes 16 pin soic 0 to +70 c MK3732-07STR mk3732-07s tape and reel 16 pin soic 0 to +70 c mk3732-07si mk3732-07si tubes 16 pin soic -40 to +85 c mk3732-07sitr mk3732-07si tape and reel 16 pin soic -40 to +85 c index area 1 2 16 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 9.80 10.00 .3859 .3937 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
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